February 8, 2010 -- -SpringSoft, Inc. today introduced a power-aware debug module for its award-winning Verdi Automated Debug System. Power-aware debug accelerates the comprehension of power intent and automates the process of visualizing, tracing and analyzing the source of power-related errors. The module is fully integrated with the hardware description language (HDL) debug capabilities of the Verdi system, the cornerstone of SpringSoft’s family of Novas Verification Enhancement products that enable engineers to do more verification in less time.

SpringSoft’s power-aware debug combines support for the United Power Format (UPF) and Common Power Format (CPF) with design comprehension tools for understanding power intent and automated debug techniques to determine whether unexpected design behavior is caused by functional logic or power-related issues. These capabilities are enabled within the Verdi environment for more efficient understanding and debug of low-power system-on-chip (SoC) designs. An early adopter release of the power-aware debug module is already in use by several top-tier global semiconductor companies.

The Verdi power-aware debug module provides full UPF and CPF source code support with the ability to import and compile data from these power design languages into SpringSoft’s Design Knowledge Database (KDB). This provides a high-level view of power intent that can be correlated with RTL design data also contained in the KDB to give a complete power-aware picture of the design structure.

An easy-to-use Power Manager browser enables engineers to visualize and annotate power intent in traditional RTL design views (source code, schematic, and waveform). Power-related constraints such as level shifter and switch rules can be easily located for each power domain and correlated to specific RTL design blocks. With the ability to cross probe between power and RTL views, engineers can readily identify the origin of power-related problems.

Leveraging the advanced RTL debug capabilities of the Verdi system, engineers can then track down the root cause of power-related behavior across RTL and power domains. The paths of signals driven by CPF/UPF code are automatically traced throughout different power domains, so debug is directed to the relevant source. Dynamic power modes/states are annotated in both RTL and power views for seamless tracing between RTL and CPF/UPF code during debug. In addition, the current power status of any signal can be quickly checked and traced to its CPF/UPF source.

The Verdi Automated Debug System is SpringSoft’s flagship product for advanced debug. It cuts debug time in half by automating the process of comprehending how complex IC and SoC designs work. The full-featured system automates behavior tracing over time with its unique analysis engines, provides a powerful set of design views to visualize and help analyze cause-and-effect relationships, and uses patented techniques to reveal the functional operation and interaction between the design, assertions and system testbench.

The Verdi Power-aware Debug Module is immediately available at U.S. list price of $5,000 for a one-year subscription license. It is fully supported with the latest release of the Verdi Automated Debug System, which is U.S. list priced at $14,000 for a one-year subscription license.

Go to the SpringSoft, Inc. website for product details.