July 15, 2010 -- The cost of SOC (system-on-chip) design continues to skyrocket, market windows continue to shrink, and design complexity continues to grow exponentially. These challenges are only a few of those that SOC designers face. In an effort to prevent major disasters, designers must ensure that the SOCs achieve design closure, which includes meeting certain key objectives, such as performance, power, and area. Design-closure objectives are often in conflict with each other, however. Designers must constantly trade off one for the other to ensure that the design stays within the enduser application’s requirements.

A typical SOC design starts with an RTL (register-transfer-level) description to capture user intent and a set of design constraints to drive implementation. The design team first verifies the RTL for correctness of functional intent through simulation and formal verification. The design then goes through a series of implementation steps, including synthesis and placement and routing, which eventually result in a GDSII (Graphic Design System 2) layout for silicon manufacturing. The quality of incoming design and the associated constraints have a large impact on the designers’ ability to reach closure. However, you can ease this process by using a series of design-quality measures starting at RTL and continuing throughout implementation, focusing on quality measures at the five stages during an integrated RTL-to-GDSII implementation flow. You can expand the concept to other stages of implementation or adapt it to other flows, including presynthesis-RTL quality; postsynthesis, postscan-netlist quality; post-timing-netlist quality; postplacement- netlist quality; or postroutenetlist quality.

By Piyush Sancheti, senior director of business development at Atrenta Inc., Sanjay Churiwala, senior director of engineering at Atrenta Inc. and Rob Knoth, senior product manager at Magma Design Automation.