July 29, 2010 -- STMicroelectronics today introduced the industry's first embedded microprocessor that couples two ARM Cortex-A9 cores with a DDR3 (Third-generation double-data rate) memory interface. Manufactured in ST's low-power 55nm HCMOS (high-speed CMOS) process technology, the SPEAr1310 delivers high computing power and customizability for multiple embedded applications together with the high level of cost competitiveness offered by system-on-chip devices.

The new microprocessor combines the unrivalled low power and multi-processing capabilities of the ARM Cortex-A9 processor core with innovative Network-on-Chip (NoC) technology. The dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent. NoC is a flexible communications architecture that enables multiple different traffic profiles while maximizing data throughput in the most performance- and power-efficient way.

Equipped with an integrated DDR2/DDR3 memory controller and a full set of connectivity peripherals, including, USB, SATA and PCIe (with integrated PHY), in addition to a Giga Ethernet MAC, ST's SPEAr1310 microprocessor targets high-performance embedded-control applications across market segments from communication and computer peripherals to industrial automation.

Cache memory coherency with hardware accelerators and I/O blocks increases throughput and simplifies software development. The Accelerator Coherency Port (ACP), coupled with the device's NoC routing capabilities, addresses the latest application requirements for hardware acceleration and I/O performance. ECC (Error Correction Coding) protection against soft and hard errors on both DRAM and L2 Cache memories dramatically improves the Mean-Time-Between-Failures for enhanced reliability.

Features:

• 2x Giga/Fast Ethernet ports (for external GMII/RGMII/MII PHY)
• 3x Fast Ethernet (for external SMII/RMII PHY)
• 3x PCIe/SATA Gen2 links (with embedded PHY)
• 1x 32-bit PCI expansion bus (up to 66 MHz)
• 2x USB 2.0 host ports with integrated PHYs
• 1x USB2.0 OTG port with integrated PHY
• 2x CAN 2.0 a/b interfaces
• 2x TDM/E1 HDLC controllers with 256/32 time slots per frame respectively
• 2x HDLC controllers for external RS485 PHYs
• I2S, UARTs, SPI, I2C ports
• HD Display controller with Touchscreen and Overlay windows capabilities
• Memory Card I/F
• Security HW Accelerator
• Secure Boot and Key Storage capabilities
• Power saving features
  

Samples of the SPEAr1310 are now available upon request to lead customers for evaluation and prototyping.

Go to the STMicroelectronics website for product details.